The present invention relates to a manufacturing method of a semiconductor device and a semiconductor device, and can be preferably used in a manufacturing method of a semiconductor device and in the semiconductor device in which, for example, an electric field effect type transistor is formed in an SOI region by using an SOI substrate.
Semiconductor devices to be applied to low power consumption devices are under development. In such a semiconductor device, an SOI substrate is used. An electric field effect type transistor is formed in a silicon layer over the SOI substrate. The electric field effect type transistor of this type is referred to as a SOTB (Silicon on Thin Buried Oxide) MISFET (Metal Insulator Semiconductor Field effect transistor). In this specification, this electric field effect type transistor is written as a “SOTB transistor”. Examples of the patent documents describing a SOTB transistor include Patent Documents 1 and 2.
In the SOTB transistor, it is required that a variation (local variation) in the microscopic or local impurity concentration of a region where the channel directly under a gate electrode is to be formed be reduced. In order to stably operate a low power consumption device with a low voltage and a low leakage current, it is necessary to reduce not only this local variation, but a global variation. The global variation means a variation in chips (processes) or in lots (processes).